/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2017-12-27 15:24:15
 *
 */


#ifndef ANLG_PHY_G1_H
#define ANLG_PHY_G1_H

#define CTL_BASE_ANLG_PHY_G1 0x40350000


#define REG_ANLG_PHY_G1_ANALOG_THM_THM0_CTRL_0                                 ( CTL_BASE_ANLG_PHY_G1 + 0x0000 )
#define REG_ANLG_PHY_G1_ANALOG_THM_THM1_CTRL_1                                 ( CTL_BASE_ANLG_PHY_G1 + 0x0004 )
#define REG_ANLG_PHY_G1_ANALOG_THM_REG_SEL_CFG_0                               ( CTL_BASE_ANLG_PHY_G1 + 0x0008 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CLKLANE_STATE_M       ( CTL_BASE_ANLG_PHY_G1 + 0x000C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_STATE_M               ( CTL_BASE_ANLG_PHY_G1 + 0x0010 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CTRL_M                ( CTL_BASE_ANLG_PHY_G1 + 0x0014 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CTRL_CSI_2P2L                  ( CTL_BASE_ANLG_PHY_G1 + 0x0018 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CLKLANE_STATE_S       ( CTL_BASE_ANLG_PHY_G1 + 0x001C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_STATE_S               ( CTL_BASE_ANLG_PHY_G1 + 0x0020 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CTRL_S                ( CTL_BASE_ANLG_PHY_G1 + 0x0024 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_RSVD                  ( CTL_BASE_ANLG_PHY_G1 + 0x0028 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_ISO_SW_EN             ( CTL_BASE_ANLG_PHY_G1 + 0x002C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXCLKLANE_DB          ( CTL_BASE_ANLG_PHY_G1 + 0x0030 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_0_DB           ( CTL_BASE_ANLG_PHY_G1 + 0x0034 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_1_DB           ( CTL_BASE_ANLG_PHY_G1 + 0x0038 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_2_DB           ( CTL_BASE_ANLG_PHY_G1 + 0x003C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_3_DB           ( CTL_BASE_ANLG_PHY_G1 + 0x0040 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATAESC_DB          ( CTL_BASE_ANLG_PHY_G1 + 0x0044 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_STATE_RX_DB           ( CTL_BASE_ANLG_PHY_G1 + 0x0048 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_DSI_RX_MISC_CTL_1     ( CTL_BASE_ANLG_PHY_G1 + 0x004C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_DSI_RX_MISC_CTL_2     ( CTL_BASE_ANLG_PHY_G1 + 0x0050 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_DATALANE_CTRL_DB      ( CTL_BASE_ANLG_PHY_G1 + 0x0054 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_ERR_DB                ( CTL_BASE_ANLG_PHY_G1 + 0x0058 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CTRL_DB               ( CTL_BASE_ANLG_PHY_G1 + 0x005C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TEST_DB               ( CTL_BASE_ANLG_PHY_G1 + 0x0060 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_ATE_TEST_CTL          ( CTL_BASE_ANLG_PHY_G1 + 0x0064 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_REG_SEL_CFG_0                  ( CTL_BASE_ANLG_PHY_G1 + 0x0068 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_CLKLANE_STATE             ( CTL_BASE_ANLG_PHY_G1 + 0x006C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_STATE0                    ( CTL_BASE_ANLG_PHY_G1 + 0x0070 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_STATE1                    ( CTL_BASE_ANLG_PHY_G1 + 0x0074 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_CTRL                      ( CTL_BASE_ANLG_PHY_G1 + 0x0078 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CTRL_CSI_4L                      ( CTL_BASE_ANLG_PHY_G1 + 0x007C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_RSVD                      ( CTL_BASE_ANLG_PHY_G1 + 0x0080 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_SW_CTRL                      ( CTL_BASE_ANLG_PHY_G1 + 0x0084 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_PHY_BIST_TEST               ( CTL_BASE_ANLG_PHY_G1 + 0x0088 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_DUMY_CTRL                    ( CTL_BASE_ANLG_PHY_G1 + 0x008C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ATE_TEST_CTL                 ( CTL_BASE_ANLG_PHY_G1 + 0x0090 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_ISO_SW_EN                 ( CTL_BASE_ANLG_PHY_G1 + 0x0094 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_REG_SEL_CFG_0                    ( CTL_BASE_ANLG_PHY_G1 + 0x0098 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_CLKLANE_STATE             ( CTL_BASE_ANLG_PHY_G1 + 0x009C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_STATE0                    ( CTL_BASE_ANLG_PHY_G1 + 0x00A0 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_STATE1                    ( CTL_BASE_ANLG_PHY_G1 + 0x00A4 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_CTRL                      ( CTL_BASE_ANLG_PHY_G1 + 0x00A8 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CTRL_CSI_2L                      ( CTL_BASE_ANLG_PHY_G1 + 0x00AC )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_RSVD                      ( CTL_BASE_ANLG_PHY_G1 + 0x00B0 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_SW_CTRL                      ( CTL_BASE_ANLG_PHY_G1 + 0x00B4 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_ISO_SW_EN                 ( CTL_BASE_ANLG_PHY_G1 + 0x00B8 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_REG_SEL_CFG_0                    ( CTL_BASE_ANLG_PHY_G1 + 0x00BC )

/* REG_ANLG_PHY_G1_ANALOG_THM_THM0_CTRL_0 */

#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_RSTN                                       BIT(14)
#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_RUN                                        BIT(13)
#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_PD                                         BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_DATA(x)                                    (((x) & 0xFF) << 4)
#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_VALID                                      BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_BG_RBIAS_MODE                              BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_TEST_SEL(x)                                (((x) & 0x3))

/* REG_ANLG_PHY_G1_ANALOG_THM_THM1_CTRL_1 */

#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_BP_MODE                                    BIT(24)
#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_BP_DATA(x)                                 (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G1_ANALOG_THM_THM_RESERVED(x)                                (((x) & 0xFFFF))

/* REG_ANLG_PHY_G1_ANALOG_THM_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_THM_THM_RSTN                               BIT(2)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_THM_THM_RUN                                BIT(1)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_THM_THM_PD                                 BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CLKLANE_STATE_M */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATECLK_M                BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSCLKNOT_M                BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RXCLKACTIVEHS_M               BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOTCLK_M            BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_STATE_M */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSESC_0_M                 BIT(18)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOT_0_M             BIT(17)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_DIRECTION_0_M                 BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_0_M               BIT(15)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATEDATA_0_M             BIT(14)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTHS_0_M                  BIT(13)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTSYNCHS_0_M              BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRESC_0_M                    BIT(11)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSYNCESC_0_M                BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRCONTROL_0_M                BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOT_1_M             BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_DIRECTION_1_M                 BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_1_M               BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATEDATA_1_M             BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTHS_1_M                  BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTSYNCHS_1_M              BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRESC_1_M                    BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSYNCESC_1_M                BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRCONTROL_1_M                BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CTRL_M */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_SHUTDOWNZ_M                   BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RSTZ_M                        BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_0_M                    BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_1_M                    BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLECLK_M                   BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_IF_SEL_M                      BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTON_M                      BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTOK_M                      BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CTRL_CSI_2P2L */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_S                       BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_L                       BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_MODE_SEL                      BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RX_RCTL(x)                    (((x) & 0xF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CLKLANE_STATE_S */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATECLK_S                BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSCLKNOT_S                BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RXCLKACTIVEHS_S               BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOTCLK_S            BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_STATE_S */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RXULPSESC_0_S                 BIT(18)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOT_0_S             BIT(17)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_DIRECTION_0_S                 BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_0_S               BIT(15)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATEDATA_0_S             BIT(14)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTHS_0_S                  BIT(13)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTSYNCHS_0_S              BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRESC_0_S                    BIT(11)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSYNCESC_0_S                BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRCONTROL_0_S                BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ULPSACTIVENOT_1_S             BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_DIRECTION_1_S                 BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_1_S               BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_STOPSTATEDATA_1_S             BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTHS_1_S                  BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSOTSYNCHS_1_S              BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRESC_1_S                    BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRSYNCESC_1_S                BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ERRCONTROL_1_S                BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CTRL_S */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_SHUTDOWNZ_S                   BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RSTZ_S                        BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_0_S                    BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_1_S                    BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLECLK_S                   BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_IF_SEL_S                      BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTON_S                      BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTOK_S                      BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_RSVD */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RESERVEDO(x)                  (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_RESERVED(x)                   (((x) & 0xFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_ISO_SW_EN */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_ISO_SW_EN                     BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXCLKLANE_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTHSCLK_DB             BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSCLK_DB                  BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXITCLK_DB              BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATECLK_DB               BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOTCLK_DB           BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_0_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_0_DB          BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTESC_0_DB             BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXLPDTESC_0_DB                BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSESC_0_DB                BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXIT_0_DB               BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXTRIGGERESC_0_DB(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXVALIDESC_0_DB               BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREADYESC_0_DB               BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_1_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_1_DB          BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTESC_1_DB             BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXLPDTESC_1_DB                BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSESC_1_DB                BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXIT_1_DB               BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXTRIGGERESC_1_DB(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXVALIDESC_1_DB               BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREADYESC_1_DB               BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_2_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_2_DB          BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTESC_2_DB             BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXLPDTESC_2_DB                BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSESC_2_DB                BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXIT_2_DB               BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXTRIGGERESC_2_DB(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXVALIDESC_2_DB               BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREADYESC_2_DB               BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATA_3_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_3_DB          BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTESC_3_DB             BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXLPDTESC_3_DB                BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSESC_3_DB                BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXULPSEXIT_3_DB               BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXTRIGGERESC_3_DB(x)          (((x) & 0xF) << 2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXVALIDESC_3_DB               BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREADYESC_3_DB               BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TXDATAESC_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXDATAESC_0_DB(x)             (((x) & 0xFF) << 24)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXDATAESC_1_DB(x)             (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXDATAESC_2_DB(x)             (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TXDATAESC_3_DB(x)             (((x) & 0xFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_STATE_RX_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXCLKESC_0_DB                 BIT(27)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXLPDTESC_0_DB                BIT(26)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXTRIGGERESC_0_DB(x)          (((x) & 0xF) << 22)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXVALIDESC_0_DB               BIT(21)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXCLKESC_1_DB                 BIT(20)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXLPDTESC_1_DB                BIT(19)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXTRIGGERESC_1_DB(x)          (((x) & 0xF) << 15)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXVALIDESC_1_DB               BIT(14)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXCLKESC_2_DB                 BIT(13)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXLPDTESC_2_DB                BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXTRIGGERESC_2_DB(x)          (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXVALIDESC_2_DB               BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXCLKESC_3_DB                 BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXLPDTESC_3_DB                BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXTRIGGERESC_3_DB(x)          (((x) & 0xF) << 1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXVALIDESC_3_DB               BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_DSI_RX_MISC_CTL_1 */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXULPSESC_0_DB                BIT(19)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXULPSESC_1_DB                BIT(18)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXULPSESC_2_DB                BIT(17)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXULPSESC_3_DB                BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXDATAESC_0_DB(x)             (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXDATAESC_1_DB(x)             (((x) & 0xFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_DSI_RX_MISC_CTL_2 */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXDATAESC_2_DB(x)             (((x) & 0xFF) << 12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RXDATAESC_3_DB(x)             (((x) & 0xFF) << 4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOT_0_DB            BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOT_1_DB            BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOT_2_DB            BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ULPSACTIVENOT_3_DB            BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_DATALANE_CTRL_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNREQUEST_0_DB              BIT(22)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_DIRECTION_0_DB                BIT(21)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNDISABLE_0_DB              BIT(20)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCERXMODE_0_DB              BIT(19)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCETXSTOPMODE_0_DB          BIT(18)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATEDATA_0_DB            BIT(17)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNREQUEST_1_DB              BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNDISABLE_1_DB              BIT(15)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCERXMODE_1_DB              BIT(14)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCETXSTOPMODE_1_DB          BIT(13)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATEDATA_1_DB            BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNREQUEST_2_DB              BIT(11)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_DIRECTION_2_DB                BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNDISABLE_2_DB              BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCERXMODE_2_DB              BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCETXSTOPMODE_2_DB          BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATEDATA_2_DB            BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNREQUEST_3_DB              BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_DIRECTION_3_DB                BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TURNDISABLE_3_DB              BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCERXMODE_3_DB              BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCETXSTOPMODE_3_DB          BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_STOPSTATEDATA_3_DB            BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_ERR_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRESC_0_DB                   BIT(19)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRSYNCESC_0_DB               BIT(18)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTROL_0_DB               BIT(17)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP0_0_DB         BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP1_0_DB         BIT(15)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRESC_1_DB                   BIT(14)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRSYNCESC_1_DB               BIT(13)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTROL_1_DB               BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP0_1_DB         BIT(11)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP1_1_DB         BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRESC_2_DB                   BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRSYNCESC_2_DB               BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTROL_2_DB               BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP0_2_DB         BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP1_2_DB         BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRESC_3_DB                   BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRSYNCESC_3_DB               BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTROL_3_DB               BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP0_3_DB         BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ERRCONTENTIONLP1_3_DB         BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_CTRL_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_SHUTDOWNZ_DB                  BIT(15)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_RSTZ_DB                       BIT(14)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLE_0_DB                   BIT(13)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLE_1_DB                   BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLE_2_DB                   BIT(11)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLE_3_DB                   BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_ENABLECLK_DB                  BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_FORCEPLL_DB                   BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_BISTON_DB                     BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_BISTDONE_DB                   BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_IF_SEL_DB                     BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DEBUG_EN_DB                       BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TRIMBG_DB(x)                  (((x) & 0xF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_TEST_DB */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTDIN_DB(x)                 (((x) & 0xFF) << 11)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTDOUT_DB(x)                (((x) & 0xFF) << 3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTEN_DB                     BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTCLK_DB                    BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_DSI_TESTCLR_DB                    BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_CSI_2P2L_ATE_TEST_CTL */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_ATE_TEST_SEL(x)                   (((x) & 0x3))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2P2LANE_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_0_M       BIT(29)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_1_M       BIT(28)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_SHUTDOWNZ_M           BIT(27)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_RSTZ_M                BIT(26)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_0_M            BIT(25)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_1_M            BIT(24)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLECLK_M           BIT(23)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_IF_SEL_M              BIT(22)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTON_M              BIT(21)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_S               BIT(20)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_L               BIT(19)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_0_S       BIT(18)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_FORCERXMODE_1_S       BIT(17)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_SHUTDOWNZ_S           BIT(16)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_RSTZ_S                BIT(15)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_0_S            BIT(14)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLE_1_S            BIT(13)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ENABLECLK_S           BIT(12)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_IF_SEL_S              BIT(11)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_BISTON_S              BIT(10)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_ISO_SW_EN             BIT(9)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTHSCLK_DB     BIT(8)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_0_DB  BIT(7)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_1_DB  BIT(6)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_2_DB  BIT(5)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TXREQUESTDATAHS_3_DB  BIT(4)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_SHUTDOWNZ_DB          BIT(3)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_IF_SEL_DB             BIT(2)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DEBUG_EN_DB               BIT(1)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_DSI_TRIMBG_DB             BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_CLKLANE_STATE */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_STOPSTATECLK                    BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RXULPSCLKNOT                    BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RXCLKACTIVEHS                   BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ULPSACTIVENOTCLK                BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_STATE0 */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RXULPSESC_0                     BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ULPSACTIVENOT_0                 BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RXULPSESC_1                     BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ULPSACTIVENOT_1                 BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RXULPSESC_2                     BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ULPSACTIVENOT_2                 BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RXULPSESC_3                     BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ULPSACTIVENOT_3                 BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_STATE1 */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_DIRECTION_0                     BIT(31)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_FORCERXMODE_0                   BIT(30)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_STOPSTATEDATA_0                 BIT(29)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_DIRECTION_1                     BIT(28)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_FORCERXMODE_1                   BIT(27)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_STOPSTATEDATA_1                 BIT(26)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_DIRECTION_2                     BIT(25)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_FORCERXMODE_2                   BIT(24)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_STOPSTATEDATA_2                 BIT(23)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_DIRECTION_3                     BIT(22)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_FORCERXMODE_3                   BIT(21)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_STOPSTATEDATA_3                 BIT(20)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSOTHS_0                      BIT(19)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSOTSYNCHS_0                  BIT(18)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRESC_0                        BIT(17)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSYNCESC_0                    BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRCONTROL_0                    BIT(15)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSOTHS_1                      BIT(14)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSOTSYNCHS_1                  BIT(13)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRESC_1                        BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSYNCESC_1                    BIT(11)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRCONTROL_1                    BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSOTHS_2                      BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSOTSYNCHS_2                  BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRESC_2                        BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSYNCESC_2                    BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRCONTROL_2                    BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSOTHS_3                      BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSOTSYNCHS_3                  BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRESC_3                        BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRSYNCESC_3                    BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ERRCONTROL_3                    BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_SHUTDOWNZ                       BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RSTZ                            BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ENABLE_0                        BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ENABLE_1                        BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ENABLE_2                        BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ENABLE_3                        BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ENABLECLK                       BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_IF_SEL                          BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_BISTON                          BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_BISTOK                          BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CTRL_CSI_4L */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_PS_PD_S                         BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_PS_PD_L                         BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RX_RCTL(x)                      (((x) & 0xF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_RSVD */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RESERVED(x)                     (((x) & 0xFFFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_SW_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_RESERVEDO(x)                    (((x) & 0xFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_PHY_BIST_TEST */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_FORCE_CSI_PHY_SHUTDOWNZ             BIT(27)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_FORCE_CSI_PHY_SHUTDOWNZ             BIT(26)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_FORCE_DSI_PHY_SHUTDOWNZ             BIT(25)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_FORCE_CSI_S_PHY_SHUTDOWNZ           BIT(24)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_FORCE_DSI_DBG_PHY_SHUTDOWNZ         BIT(23)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_2P2L_TESTCLR_M_EN               BIT(22)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_2P2L_TESTCLR_M_SEL              BIT(21)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_2P2L_TESTCLR_M                  BIT(20)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_2P2L_TESTCLR_S_EN               BIT(19)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_2P2L_TESTCLR_S_SEL              BIT(18)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_2P2L_TESTCLR_S                  BIT(17)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_REFDIV(x)                      (((x) & 0xF) << 13)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_TXREQHSCLK_DB                  BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_BERT_RXBYTECLK_SEL(x)          (((x) & 0x3) << 10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_BERT_D0_TXSRC_SEL(x)           (((x) & 0x3) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_BERT_D1_TXSRC_SEL(x)           (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_BERT_D2_TXSRC_SEL(x)           (((x) & 0x3) << 4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_BERT_D3_TXSRC_SEL(x)           (((x) & 0x3) << 2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_BERT_TEST_SEL                  BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_MIPI_BERT_REFCLK_EN                 BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_DUMY_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_ANALOG_CSI_DUMY_IN(x)               (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_ANALOG_CSI_DUMY_OUT(x)              (((x) & 0xFFFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ATE_TEST_CTL */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_ATE_TEST_SEL                        BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_4L_ISO_SW_EN */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_CSI_ISO_SW_EN                       BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_4LANE_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_FORCERXMODE_0           BIT(16)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_FORCERXMODE_1           BIT(15)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_FORCERXMODE_2           BIT(14)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_FORCERXMODE_3           BIT(13)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_SHUTDOWNZ               BIT(12)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_RSTZ                    BIT(11)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_ENABLE_0                BIT(10)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_ENABLE_1                BIT(9)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_ENABLE_2                BIT(8)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_ENABLE_3                BIT(7)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_ENABLECLK               BIT(6)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_IF_SEL                  BIT(5)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_BISTON                  BIT(4)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_PS_PD_S                 BIT(3)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_PS_PD_L                 BIT(2)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_RX_RCTL                 BIT(1)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_ISO_SW_EN               BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_CLKLANE_STATE */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_STOPSTATECLK                    BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_RXULPSCLKNOT                    BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_RXCLKACTIVEHS                   BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ULPSACTIVENOTCLK                BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_STATE0 */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_RXULPSESC_0                     BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_RXULPSESC_1                     BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ULPSACTIVENOT_0                 BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ULPSACTIVENOT_1                 BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_STATE1 */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_DIRECTION_0                     BIT(15)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_FORCERXMODE_0                   BIT(14)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_STOPSTATEDATA_0                 BIT(13)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_DIRECTION_1                     BIT(12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_FORCERXMODE_1                   BIT(11)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_STOPSTATEDATA_1                 BIT(10)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRSOTHS_0                      BIT(9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRSOTSYNCHS_0                  BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRESC_0                        BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRSYNCESC_0                    BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRCONTROL_0                    BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRSOTHS_1                      BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRSOTSYNCHS_1                  BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRESC_1                        BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRSYNCESC_1                    BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ERRCONTROL_1                    BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_SHUTDOWNZ                       BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_RSTZ                            BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ENABLE_0                        BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ENABLE_1                        BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ENABLECLK                       BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_IF_SEL                          BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_BISTON                          BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_BISTOK                          BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CTRL_CSI_2L */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_PS_PD_S                         BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_PS_PD_L                         BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_RX_RCTL(x)                      (((x) & 0xF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_RSVD */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_RESERVED(x)                     (((x) & 0xFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_SW_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_RESERVEDO(x)                    (((x) & 0xFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_2L_ISO_SW_EN */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_CSI_ISO_SW_EN                       BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_CSI_2LANE_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_FORCERXMODE_0           BIT(12)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_FORCERXMODE_1           BIT(11)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_SHUTDOWNZ               BIT(10)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_RSTZ                    BIT(9)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_ENABLE_0                BIT(8)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_ENABLE_1                BIT(7)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_ENABLECLK               BIT(6)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_IF_SEL                  BIT(5)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_BISTON                  BIT(4)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_PS_PD_S                 BIT(3)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_PS_PD_L                 BIT(2)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_RX_RCTL                 BIT(1)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_CSI_2LANE_CSI_ISO_SW_EN               BIT(0)


#endif /* ANLG_PHY_G1_H */

